Many conventional CMOS latch circuits use a pass-gate to clock data into cross-coupled inverters. The term "pass-gate" refers to the function of passing an input signal in response to a control signal applied to the gate of a device. The pass-gate may be either a single NFET device, a single PFET device, or a parallel NFET-PFET pair. In such a conventional latch, the feedback inverter of the cross-coupled inverters must be smaller than the data input inverter so that the data inverter can overdrive the feedback inverter in order to change the state of the latch. The requirement of different sizes for the inverters makes it difficult to implement the latch in a gate array design where only one device size is available.
There are many latch designs available in the prior art. Examples of such prior art latch circuit designs are discussed below.
U.S. Pat. No. 4,277,699 discloses a shift register latch circuit including a polarity hold latch and a set/reset latch. The latches can be clocked with separate non-overlapping clock trains and therefore conform to the so-called Level Sensitive Scan Design (LSSD) rules which enable logic networks embodied in large scale integrated semiconductors to be adequately tested. FIG. 4 of the patent shows how the shift register latch may be implemented with AND/OR/INVERT circuits.
IBM Technical Disclosure Bulletin, Vol. 27, No. 7B, December 1984, pp. 4538-4539 discloses a CMOS LSSD shift register latch which can be implemented in a master slice design without transfer or pass gates to thereby enhance testability. In particular, this reference discloses a two-stage polarity-hold version in which the memory function of the latch is performed by standard CMOS cross-coupled pairs.
IBM Technical Disclosure Bulletin Vol. 27, No. 1B, June 1984, pp. 663-664 discloses a high speed CMOS latch circuit in which clock and data pulses are directly available to the output buffer (CMOS inverter) without first setting the latch.
IBM Technical Bulletin Vol. 27, No. 10B, March 1985, pp. 6098-6099 discloses a LSSD-compatible latch. The latch circuit includes two stages of AND/OR/INVERT circuits controlled by two sets of input controls.
U.S. Pat. No. 4,568,842 discloses a D-Latch CMOS circuit for holding a logic signal in response to a control pulse.
IBM Technical Bulletin Vol. 16, No. 7, December 1973, pp. 2289-2290 discloses a gated inverter using CMOS transistors.
U.S. Pat. No. 3,619,644 discloses a frequency dividing circuit having a logic structure satisfying specified Boolean relationships.
Although various latch circuits are known in the art, it is important to decrease, as much as possible, the amount of current required to change the state of the latch. As discussed above, many latch designs employ data inverters which can overdrive the feedback inverter to change the latch state. With this process a significant amount of device current is needed to force the feedback loop from a first state to a second opposite state. Since the switching speed is proportional to the load provided between the inverter nodes of the latch, a large load will decrease the switching speed of the latch. With increasing levels of integration, this is becoming increasingly important. More particularly, as levels of integration increase, so does the number of latches required to switch in a given cycle.